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semiconductor group 125 01.95 512kx8-bit dynamic ram advanced information ? 512 288 words by 8-bit organization ? 0 to 70 ?c operating temperature ? fast access and cycle time ras access time: 60 ns (-60 version) 70 ns (-70 version) 80 ns (-80 version) cas access time: 20 ns cycle time: 110 ns (-60 version) 130 ns (-70 version) 150 ns (-80 version) ? fast page mode cycle time 45 ns (-60 version) 45 ns (-70 version) 50 ns (-80 version) ? single + 5 v ( 10 %) supply with a built-in v bb generator ordering information type ordering code package descriptions hyb 514800bj-60 Q67100-Q849 p-soj-28-2 dram (access time 60 ns) hyb 514800bj-70 q67100-q850 p-soj-28-2 dram (access time 70 ns) hyb 514800bj-80 q67100-q851 p-soj-28-2 dram (access time 80 ns) hyb 514800bj -60/-70/-80 ? low power dissipation max. 605 mw active (-60 version) max. 550 mw active (-70 version) max. 468 mw active (-80 version) ? standby power dissipation: 11 mw standby standby (ttl) 5.5 mw max.standby (cmos) ? output unlatched at cycle end allows two- dimensional chip selection ? read, write, read-modify write, cas-before- ras refresh, ras-only refresh, hidden refresh, fast page mode capability ? all inputs and outputs ttl-compatible ? 1024 refresh cycles / 16 ms ? plastic packages: p-soj-28-2 400 mil width
semiconductor group 126 the hyb 514800bj is the new generation dynamic ram organized as 512 288 words by 8-bit. the hyb 514800bj utilizes cmos silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. multiplexed address inputs permit the hyb 514800bj to be packed in a standard plastic 400mil wide p-sopj-28 package. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. system oriented feature include single + 5 v ( 10 %) power supply, direct interfacing with high performance logic device families such as schottky ttl. pin definitions and functions pin configuration (top view) a0-a8,a9r address input ras row address strobe cas column address strobe write read/write input oe output enable i o1 - i o8 data input/output n.c. no connection v cc power supply (+ 5 v) v ss ground (0 v) p-soj-28-2 ( 400 mil width) hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 127 block diagram hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 128 absolute maximum ratings operating temperature range ............................................................................................0 to 70 ? c storage temperature range......................................................................................C 55 to + 150 ?c soldering temperature .......................................................................................................... ..260 ?c soldering time ................................................................................................................. ............10 s input/output voltage ........................................................................................................ C 1 to + 7 v power supply voltage ..................................................................................................... C 1 to + 7 v data out current (short circuit) ............................................................................................... .50ma note: stresses above those listed under "absolute maximum ratings" may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 ?c, v ss = 0 v, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.4 6.5 v 1) input low voltage v il C 1.0 0.8 v 1) output high voltage ( i out = C 5 ma) v oh 2.4 C v 1) output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1) input leakage current, any input (0 v < v in < 7, all other input = 0 v) i i (l) C 10 10 m a 1) output leakage current (do is disabled, 0 < v out < v cc ) i o(l) C 10 10 m a 1) average v cc supply current -60 version -70 version -80 version i cc1 C C C 110 100 90 ma 2) 3) standby v cc supply current (ras = cas = v ih ) i cc2 C2maC average v cc supply current during ras-only refresh cycles -60 version -70 version -80 version i cc3 C C C 110 100 90 ma 2) average v cc supply current during fast page mode operation -60 version -70 version -80 version i cc4 C C C 70 60 50 ma 2) 3) hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 129 standby v cc supply current (ras = cas = v cc C 0.2 v) i cc5 C1ma 1) average v cc supply current during cas before ras refresh mode -60 version -70 version -80 version i cc6 C C C 110 100 90 ma 2) dc characteristics (contd) t a = 0 to 70 ?c, v ss = 0 v, v cc = 5 v 10 %, t t = 5 ns parameter symbol limit values unit test condition min. max. hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 130 ac characteristics 4) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -60 -70 -80 min. max. min. max. min. max. random read or write time t rc 110 C 130 C 150 C ns read-write cycle time t rwc 165 C 185 C 205 C ns fast page mode cycle time t pc 45 C 45 C 50 C ns fast page mode read/write cycle time t prwc 100 C 100 C 105 C ns access time from ras 6) 11) t rac C60C70C80ns access time from cas 6) 11) t cac C20C20C20ns access time from column address 6) 12) t aa C30C35C40ns access time from cas precharge 6) t cpa C40C40C45ns cas to output in low-z 6) t clz 0C0C0Cns output buffer turn-off delay from cas 7) t off 020020020ns transition time (rise and fall) 5) t t 350350350ns ras precharge time t rp 40 C 50 C 60 C ns ras pulse width t ras 60 10000 70 10000 80 10000 ns ras pulse width in fast page mode t rasp 60 200000 70 200000 80 200000 ns cas pulse width t cas 20 10000 20 10000 20 10000 ns ras hold time t rsh 20 C 20 C 20 C ns cas hold time t csh 60 C 70 C 80 C ns ras hold time from cas precharge (fast page mode) t rhcp 40 C 45 C 50 C ns cas precharge to write delay time (fpm read-modify-write) t cpwd 60 C 65 C 70 C ns hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 131 ras to cas delay time 11) t rcd 20 40 20 50 20 60 ns ras to column address delay time 12) t rad 15 30 15 35 15 40 ns cas to ras precharge time t crp 5C5C10Cns cas precharge time t cp 10 C 10 C 10 C ns row address setup time t asr 0C0C0Cns row address hold time t rah 10 C 10 C 10 C ns column address setup time t asc 0C0C0Cns column address hold time t cah 15 C 15 C 15 C ns column address to ras lead time t ral 30 C 35 C 40 C ns read command setup time t rcs 0C0C0Cns read command hold time 8) t rch 0C0C0Cns read command hold time ref. to ras 8) t rrh 0C0C0Cns write command hold time t wch 10 C 15 C 15 C ns write command hold time ref. to ras t wcr 50 C 55 C 60 C ns write command pulse width t wp 10 C 15 C 15 C ns write command to ras lead time t rwl 20 C 20 C 20 C ns write command to cas lead time t cwl 20 C 20 C 20 C ns data setup time 9) t ds 0C0C0Cns ac characteristics (contd) 4) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -60 -70 -80 min. max. min. max. min. max. hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 132 data hold time 9) t dh 15 C 15 C 15 C ns refresh period t ref C16C16C16ms write command setup time 10) t wcs 0C0C0Cns cas to write delay time 10) t cwd 50 C 50 C 50 C ns ras to write delay time 10) t rwd 90 C 100 C 110 C ns column address to write delay time 10) t awd 60 C 65 C 70 C ns cas setup time (cbr cycle) t csr 5C5C5Cns cas hold time (cbr cycle) t chr 15 C 15 C 15 C ns ras to cas precharge time t rpc 0C0C0Cns cas precharge time (cas before ras counter test cycle) t cpt 30 C 40 C 40 C ns write to ras precharge time (cbr cycle) t wrp 10 C 10 C 10 C ns write to ras hold time (cbr cycle) t wrh 10 C 10 C 10 C ns oe command hold time t oeh 20 C 20 C 20 C ns oe acces time t oea C20C20C20ns ras hold time referenced to oe t roh 10 C 10 C 10 C ns output buffer turn-off delay from oe t oez 020020020ns data to cas low delay 14) t dzc 0C0C0Cns ac characteristics (contd) 4) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -60 -70 -80 min. max. min. max. min. max. hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 133 data to oe low delay 14) t dz0 0C0C0Cns cas high to data delay 15) t cdd 20 C 20 C 20 C ns oe high to data delay 15) t odd 20 C 20 C 20 C ns cas hold time after oe low t oech 20 C 20 C 20 C ns capacitance t a = 0 to 70 ?c; v cc = 5 v 10 %; f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a9) c i1 C5pf input capacitance ( ras, cas, we) c i2 C7pf output capacitance ( i o1 to i o8) c io C7pf ac characteristics (contd) 4) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -60 -70 -80 min. max. min. max. min. max. hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 134 notes: 1) all voltages are referenced to v ss 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 , i cc4 depend on output loading. 4) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas-before-ras initialization cycles instead of 8 ras cycles are required. 5) v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 6) measured with a load equivalent to 2 ttl loads and 100 pf. 7) t off (max.), t oez (max.) defines the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 8) either t rch or t rrh must be satisfied for a read cycle. 9) these parameters are references to the cas leading edge in early write and to the write leading edge in read-write cycles. 10) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.), t cwd > t cwd (min.) and t awd > t awd (min.), the cycle is a read- write cycle and i/ o will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of i /o (at access time) is indeterminate. 11) operation within the t rcd (max.) limit ensure that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rad is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 12) operation within the t rad (max.) limit ensured that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 13) ac measurements assume t t = 5 ns. 14) either t dzc or t dzo must be satisfied. 15) either t cdd or t odd must be satisfied. hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 135 read cycle row address column address row address valid data out ras cas a0 - a9 write oe i/o1-i/o8 (inputs) (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l i/o1-i/o8 hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 136 write cycle (early write) t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column address address row row address t rah t wcs h or l i/o1-i/o8 (inputs) i/o1-i/o8 (outputs) hyb 514800bj -60/-70/-80 512k x 8 dram ras cas a0 - a9 write oe v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr
semiconductor group 137 write cycle ( oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row address t dzc h or l hi-z hi-z column address address row t asc t rad t ral t cah t rah i/o1-i/o8 i/o1-i/o8 (outputs) hyb 514800bj -60/-70/-80 512k x 8 dram ras cas a0 - a9 write oe (inputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr
semiconductor group 138 read-write (read-modify-write) cycle row address row address t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o1-i/o8 (outputs) v oh v ol v ih v il v ih v il i/o1-i/o8 (inputs) oe write v ih v il t asr column address t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il hyb 514800bj -60/-70/-80 512k x 8 dram ras cas a0 - a9 v ih v il
semiconductor group 139 fast page mode read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol write oe i/o1-i/o8 (inputs) i/o1-i/o8 (outputs) data in data in data in data out out data data out address row column address address column address row address t rasp t csh column t cpwd t cpwd h or l a0-a9 t oez hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 140 fast page mode read cycle t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t rac t cac valid data out data out data out valid valid column address address addr address column row row ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write a0-a9 cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l t rhcp t rch v oh v ol column address hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 141 fast page mode early write cycle t rasp t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column address address address column column row addr valid data in valid valid data in data in column address hi-z ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write a0-a9 cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 142 ras-only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row address row address hi-z a0-a9 ras cas i/o1-i/o8 (outputs) h or l hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 143 cas-before- ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o8 (outputs) oe write cas v oh v ol i/o1-i/o8 (inputs) hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 144 hidden refresh cycle (read) ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write a0-a9 cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row address column address row addr hi-z v oh v ol hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 145 hidden refresh cycle (early write) ras i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) oe write v ih v il a0-a9 v ih v il v ih v il v ih v il cas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc address row addr row address valid data hi-z column v oh v ol hyb 514800bj -60/-70/-80 512k x 8 dram
semiconductor group 146 cas-before- ras refresh counter test cycle t csr t asr t asc t chr t cpt t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t odd t dh t wrh t wrp t oez t rwl t cwl t awd t cwd t wp t rcs t cac t oea t oeh t aa t clz t dh t dzo t ds t dzc t cac v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o1-i/o8 (inputs) ras i/o1-i/o8 (inputs) oe write a0-a9 cas i/o1-i/o8 (outputs) i/o1-i/o8 (outputs) i/o1-i/o8 (inputs) write oe write oe i/o1-i/o8 (outputs) column address row address data in valid data out valid data in hi-z hi-z hi-z read cycle read-modify-write cycle write cycle t rrh t rch d.out hyb 514800bj -60/-70/-80 512k x 8 dram

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